High voltage (HV) semiconductor devices such as diodes, transistors and IGBTs insulated gate bipolar transistors), usually include more or less heavily doped semiconductor areas so as to define a pn junction. In HV applications, which are to understood as applications requiring the handling von approximately 60 V and higher, such as 100V and more, for instance up to several hundred Volts, usually contain a dedicated pn junction, which depletes in the off-state and supports the off-state voltage, i.e., the depleted region electrically isolates the p-doped region and the n-doped region from each other. This part is called “drift region”, “lowly-doped region” or “voltage supporting region”. To those skilled in the art, the engineering of this drift region is well-established.
The high voltage device is embedded in a semiconductor substrate or material, which is normally held at a low voltage. For this reason high voltage semiconductor devices also contain isolation regions, which electrically isolate the device from the surrounding substrate. These isolation regions ensure that the high voltage is contained within the high voltage device and that the high voltage does not negatively impact the surrounding devices and the package.
Electrical isolation is achieved either by reverse-biased pn-junctions or by dielectric materials. Junction isolation utilizes similar lowly-doped regions as the drift region of the HV device. In order to be effective these isolation areas must have a higher voltage carrying capability than the interior device. In this way the voltage rating is given by the interior device only. For high voltages beyond about 100V large radii of curvature are required at respective “corners” of the interface between the interior device and the isolation region so as to minimize 2-dimensional (2D) and 3D effects of the electric field distribution which will otherwise limit the voltage carrying capability of the junction isolation area. Such curved sections with increased radii of curvature surrounding the HV device therefore increase the area requirement in the substrate for the HV device.
For lateral high voltage devices such as LDMOS, LIGBT, the lowly-doped drift region not only needs to be isolated from the surrounding substrate. The drift region also needs to be terminated in such a way that the carefully engineered field or potential distribution is not altered, since only this case the full voltage rating of the HV device can be realized. In junction isolation this requirement is achieved by rounded and oval portions commonly referred to as racetrack design. A disadvantage of these racetrack portions is that the required large inner radii increase the size of the core device. In particular, the pitch of lateral HV devices becomes larger than predicted from 2D considerations. Hence, great efforts are being made to improve this fundamental design requirement of junction isolation.
Another technique to isolate the device and terminate the drift region is dielectric isolation. Here, the task of isolation and drift region termination is fundamentally simpler. Vertical isolation is realized by using SOI (Silicon on Insulator) material, which contains a BOX (Buried Oxide) layer between the active top layer and the handle wafer substrate. Lateral isolation is achieved by forming oxide filled trenches or field oxide reaching all the way down to the BOX.
An efficient electric insulation can be achieved with relatively small geometries, due to the high electric field strength of common dielectric materials, such as silicon dioxide, silicon nitride and the like. Also, large radii of curvature are not strictly required as only the electric field strength needs to be considered, while 2D and 3D effects according to semiconductor device physics may be neglected due to the dielectric nature of the isolating material. Thus the area consumption of dielectric isolation and termination is small, when compared to junction isolation.
In thin-film SOI, with a thickness of the top silicon layer on the order of 1 μm or less, shallow trench isolation (STI) or local oxidation of silicon (LOCOS) is used to form the lateral isolation and termination. This form of isolation has practically no limitation on the width of the isolation structure, as shown in FIG. 1 and FIG. 2.
FIG. 1 schematically illustrates a cross-sectional view of a semiconductor device 1 that comprises a substrate 4, for instance a handle wafer, a buried oxide layer 3 and a silicon layer 2 formed on the buried oxide layer 3. Furthermore, a trench 5 is formed in the silicon layer 2 and extends to the buried oxide layer 3. Hence, the depth 5d of the trench 5 substantially corresponds to the thickness of the silicon layer 2, when a pronounced etching into the buried oxide layer 3 has been avoided during the preceding patterning process for forming the trench 5. As discussed above, the trench 5 has also a width 5w that is appropriate for providing the desired insulating effect after being filled with a dielectric material, such as silicon dioxide. As discussed above, for a thin-film SOI architecture the width 5w of the trench 5 is typically significantly greater than the depth 5d thereof. The trench 5 can be fabricated on the basis of well-established manufacturing techniques including lithography and etch techniques for etching material of the silicon layer 2 selectively to an etch mask and the buried oxide layer 3.
FIG. 2 schematically illustrates the device 1 at a further advanced manufacturing phase, in which the trench 5 is filled with a dielectric material 6, such as silicon dioxide. The deposition of the material 6 is accomplished by CVD (chemical vapour deposition), and the like using well-known deposition recipes. As illustrated, the material 6 can be deposited with a thickness 6d that is greater than the depth 5d of the trench 5, due to the moderately low depth 5d of the thin-film SOI configuration, thereby enabling a complete and reliable filling of the trench 5, since the filling process, at least in the centre of the trench 5, advances from bottom to top, while the growth of the material 6 from the sidewalls is less pronounced due to the small aspect ratio defined by the depth 5d to the width 5w. 
Thus, by using the shallow but wide trench 5 filled with the material 6 as an isolation structure, lateral HV devices can efficiently be isolated from the surrounding material of the layer 2 and therefore can be readily implemented into a thin-film SOI technology.
On the other hand, when using deep trenches for isolation, the width of such trenches is limited to a few microns. This situation is due to the fact that filling the trenches with dielectric layers is realized by depositing such layers on the trench sidewalls, as will be explained with reference to FIGS. 3 and 4.
FIG. 3 schematically illustrates a cross-section view of the semiconductor device 1 according to a thick-film SOI architecture. As illustrated, the device 1 comprises the trench 5 as a deep trench due to an increased thickness of the silicon layer 2, which may range from several μm to several tens of μm. In the example shown, the width 5w is substantially smaller than the depth 5d of the trench 5 in FIG. 3 in order to enable a reliable filling of the trench 5 with a practicable thickness of a dielectric material.
FIG. 4 schematically illustrates the device 1 according to the thick-film SOI architecture, wherein the trench 5 is filled with the dielectric material 6, which has now a thickness 6d that is at most half the width 5d. Hence, during the deposition process for forming the material 6 the trench 5 is filled from the sidewalls, thereby allowing a complete filling with the thickness 6d of the material 6 being less than the depth 5d of the trench 5. In this case, however, the width 5w is restricted to moderately small values.
As explained above with reference to FIG. 1 and FIG. 2, very wide trenches would require very thick dielectric films to fill relatively deep trenches, but this is expensive and to leads to difficulties during standard CMOS manufacturing due to stress that may be created in the dielectric material during the deposition thereof. Hence, it is very difficult to fill wide and deep trenches, unless creating a severe topography.
FIG. 5 schematically illustrates the device 5 when the trench 5 represents a deep and moderately wide trench. When “filling” the trench 5 with the dielectric material 6 having a thickness 6d that is similar to the thickness 6d of FIG. 4, a hole of gap 6a remains after planarization and such surfaces are very difficult to be manufactured in a standard planar semiconductor process. Thus, the width 5w of the deep trench 5 is limited to twice the dielectric layer thickness 6d at best. Again, this property of DTI (deep trench isolation) is a fundamental contrast to STI (shallow trench isolation), which fill from the bottom and thus have no width constriction, as is explained above with reference to FIG. 1 and FIG. 2.
For a purely electric HV isolation, this width limitation of a deep trench is not an issue. For example, a one micron wide oxide-filled trench can isolate several 100's of volts.
However, when using an isolation trench for the lateral termination of depleted drift regions the limited width of the trench degrades the achievable breakdown voltage. The semiconductor area outside the HV device acts as a field plate and changes the potential distribution in the drift region, as will be described with reference to FIGS. 6 to 9.
FIG. 6 schematically illustrates a top view of a conventional device 1, which comprises a HV element in the form of a PIN (p-doped, intrinsic, n-doped) diode 7, which is laterally isolated by the isolation structure 5 having wide width. Moreover, as previously discussed, the diode 7 is vertically isolated by a buried oxide layer (not shown). The diode 7 represents a HV device, i.e., a device that may be operated with voltages of 100 V and higher. The diode 7 comprises a p-doped region 7a and an n-doped region 7c each having a dopant concentration as required for obtaining the desired diode functional behaviour. Moreover, a drift region 7b is laterally positioned between the regions 7a, 7c. As discussed above, the drift region 7c typically has a lower dopant concentration compared to the regions 7a and 7c so as to allow a depleted area to form upon applying a reverse bias voltage. The depletion zone in the drift region 7b thus provides for the desired electric field strength or dielectric strength in the reverse bias mode.
FIG. 7 schematically illustrates the device 1, when the diode 7 is operated in a reverse bias mode, wherein uniformly spaced potential lines 8 (lines of constant electric potential) allow the highest breakdown voltage V1, which is physically possible in this arrangement. That is, the isolation structure 5 is provided with a sufficiently great width so as to not affect the distribution of the potential lines 8.
FIG. 8 depicts the device 1 when comprising the isolation structure 5 based on a reduced width 5w, i.e., the isolation structure 5 represents a narrow trench isolation that separates the device 7 from the surrounding semiconductor layer 2, which may be provided in the form of p-doped material. The doping of layer 2 is of less importance.
FIG. 9 shows the device 1 in the reverse bias mode, wherein the potential lines 8 crowd around the region 7c, which may be at a high yet reduce positive voltage compared to the arrangement of FIG. 7. This field crowding in the vicinity of the region 7c thus leads to a substantially smaller breakdown voltage V2 due to the increased distance of potential lines 8 in the drift region 7b in this configuration compared to the substantially non-influenced configuration described with reference to FIG. 7.
FIG. 10 schematically illustrates the device 1, wherein the trench isolation structure 5 has an increased width at least an area adjacent to the drift region 7b. In order to significantly reduce the influence of the isolation structure 5 on the finally obtained dielectric strength of the drift region 7b in the reverse bias mode, the width 5w is selected to be at least in the range or order of the drift region width 7w. In this case the potential lines are uniform in reverse bias mode and the electric field is uniform and hence, the breakdown voltage is as high as V1 in FIG. 7.
FIG. 11 illustrates the device 1 in the above described arrangement. That is, the potential lines 8 may have a substantially equal spacing within the drift region 7b and the adjacent portion of the trench isolation structure 5 having the width 5w, thereby providing for the desired high dielectric strength of the drift region 7b. 
In thick SOI technologies, however, it is very difficult to terminate the drift region 7b dielectrically using deep trenches, as is shown in FIG. 11, because they can not be filled with a dielectric material without creating undesired topography or causing significant stress, as previously discussed. Hence, junction isolation is commonly used to terminate the drift region in thick-film SOI technologies and therefore, the same area penalty applies as in HV bulk technologies. Additionally, the DTI of reduced width is then used to isolate the internally junction-terminated HV device dielectrically to the substrate.